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| EN27LV020 / EN27LV020B EN27LV020 / EN27LV020B 2Megabit Low Voltage EPROM (256K x 8) FEATURES * Read Access Time: * High-Reliability CMOS Technology * Latch-Up Immunity to 100mA from -1V to VCC + 1V * Two-Line Control ( OE & CE ) * Standard Product Identification Code * JEDEC Standard Pinout * 32-pin PDIP * 32-pin PLCC * 32-pin TSOP (Type 1) * Commercial and Industrial Temperature Ranges -90ns, -120ns, -150ns, -200ns * Single +3.3V Power Supply -Regulated power supply 3.0V - 3.6V (EN27LV020) -Unregulated power supply 2.7V - 3.6V (EN27LV020B for battery operated systems) * Programming Voltage +12.75V * QuikRiteTM Programming Algorithm * Typical programming time 20s * Low Power CMOS Operation * 1A Standby (Typical) * 15mA Operation (Max.) * CMOS- and TTL-Compatible I/O GENERAL DESCRIPTION The EN27LV020 / EN27LV020B is a low-voltage, low-power 2-Megabit, 3.3V one-timeprogrammable (OTP) read-only memory (EPROM). Organized into 256K words with 8 bits per word, it features QuikRiteTM single-address location programming, typically at 20s per byte. Any byte can be accessed in less than 90ns. The EN27LV020 / EN27LV020B has separate Output Enable ( OE ) and Chip Enable ( CE ) controls which eliminate bus contention issues. The EN27LV020 has a Vcc tolerance range of 3.0V to 3.6 V, making it suitable for use in systems that have regulated power supplies. The EN27LV020B has a Vcc tolerance range of 2.7 V to 3.6V, making it an ideal device for battery operated systems. FIGURE 1. PDIP Pin Name A0-A17 DQ0-DQ7 CE OE PGM Function Addresses Outputs Chip Enable Output Enable Program Strobe A17 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 1 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B FIGURE 2. TSOP TSOP A17 EN27LV020/ EN27LV020B FIGURE 3. PLCC P L C C T o p V ie w A12 A16 Vcc A17 A1 5 Vpp PGM 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 2 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B FIGURE 4. BLOCK DIAGRAM CE PGM OE CONTROL LOGIC INPUT/ OUTPUT BUFFERS DQ0 - DQ7 8 Y-DECODER A0 - A17 ADDRESS INPUTS X-DECODER 1024 Y-SELECT 2048 2M BIT CELL MATRIX Vcc Vss Vpp FUNCTIONAL DESCRIPTION THE QUIKRITETM PROGRAMMING OF THE EN27LV020 / EN27LV020B When the EN27LV020 / EN27LV020B is delivered, the chip has all 2M bits in the "ONE", or HIGH state. "ZEROs" are loaded into the EN27LV020 / EN27LV020B through the procedure of programming. The programming mode is entered when 12.75 0.25V is applied to the VPP pin, OE is at VIH , and CE and PGM are at VIL. For programming, the data to be programmed is applied with 8 bits in parallel to the data pins. The QUIKRITE programming flowchart in Figure 5 shows Eon's interactive programming algorithm. The interactive algorithm reduces programming time by using 20 s to 100 s programming pulses and giving each address only as many pulses as is necessary in order to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data is not verified, additional pulses are given until it is verified or until the maximum number of pulses is reached. This process is repeated while sequencing through each address of the EN27LV020 / EN27LV020B. This part of the programming algorithm is done at VCC = 6.25V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. This ensures that all bits have sufficient margin. After the final address is completed, the entire EPROM memory is read at VCC = VPP = 5.25 0.25V to verify the entire memory. EN27LV020 / EN27LV020B can be programmed using the same programming algorithm as the 5V Read EPROM EN27C020. 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 TM 3 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B PROGRAM INHIBIT MODE Programming of multiple EN27LV020 / EN27LV020B in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE , all like inputs of the parallel EN27LV020 / EN27LV020B may be common. A TTL low-level program pulse applied to an EN27LV020 / EN27LV020B CE input with VPP = 12.75 0.25V, PGM LOW, and OE HIGH will program that EN27LV020 / EN27LV020B. A high-level CE input inhibits the other EN27LV020 / EN27LV020B from being programmed. PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determining that they were correctly programmed. The verification should be performed with OE and CE at VIL, PGM at VIH, and VPP at its programming voltage. AUTO PRODUCT IDENTIFICATION The Auto Product Identification mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25C 5C ambient temperature range that is required when programming the EN27LV020 / EN27LV020B. To activate this mode, the programming equipment must force 12.0 V 0.5V on address line A9 of the EN27LV020 / EN27LV020B. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH, when A1 = VIH. All other address lines must be held at VIL during Auto Product Identification mode. Byte 0 (A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device code. For the EN27LV020 / EN27LV020B these two identifiers bytes are given in the Mode Select Table. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. When A1 = VIL, the EN27LV020 / EN27LV020B will read out the binary code of 7F, continuation code, to signify the unavailability of manufacturer ID codes. 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 4 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B READ MODE The EN27LV020 / EN27LV020B has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable ( CE ) is the power control and should be used for device selection. Output Enable ( OE ) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs (tOE) after the falling edge of OE , assuming the CE has been LOW and addresses have been stable for at least tACC - tOE. STANDBY MODE The EN27LV020 / EN27LV020B has CMOS standby mode which reduces the maximum VCC current to 10A. It is placed in CMOS standby when CE is at VCC 0.3 V. The EN27LV020 / EN27LV020B also has a TTL-standby mode which reduces the maximum VCC current to 0.6 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a two-line control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selection function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1F ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7F bulk electrolytic capacitor should be used between VCC and VSS for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 5 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B MODE SELECT TABLE Mode Read Output Disable Standby (TTL) Standby (CMOS) Program (4) Program Verify Program Inhibit Manufacturer Code Device Code (3) (3) CE VIL VIL VIH VCC 0.3V VIL VIL VIH VIL VIL OE VIL PGM (2) X A0 X X X X X X X VIL VIH A1 X X X X X X X VIH VIH A9 X X X X X X X VH VH (1) (1) VPP VCC VCC VCC VCC VPP VPP VPP VCC VCC Output DOUT High Z High Z High Z DIN DOUT High Z 1C 02 VIH X X VIH VIL X VIL VIL X X X VIL VIH X X X NOTES: 1) VH = 12.0V 0.5V 2) X = Either VIH or VIL 3) For Manufacturer Code and Device Code, A1 = VIH When A1 = VIL, both codes will read 7F 4) See DC Programming Characteristics for VPP voltage during programming EON'S STANDARD PRODUCT IDENTIFICATION CODE Pins Code Manufacturer Device Type Continuation A0 0 1 0 1 A1 1 1 0 0 DQ7 0 0 0 0 DQ6 0 0 1 1 DQ5 0 0 1 1 DQ4 1 0 1 1 DQ3 1 0 1 1 DQ2 1 0 1 1 DQ1 0 1 1 1 DQ0 0 0 1 1 Hex Data 1C 02 7F 7F 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 6 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B FIGURE 5. QUIKRITETM PROGRAMMING FLOW CHART 20 NOTE 1 NOTE 1: Either 100s or 20s pulse. 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 7 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to VSS All pins except A9, VPP, VCC A9, VPP VCC -65YC to +125YC -40YC to +85YC -0.6V to VCC + 0.5V -0.6V to +13.5V -0.6V to +7.0V OPERATING RANGES Commercial (C) Case Temperature(Tc) Industrial (I) Case Temperature(Tc) 0YC to +70YC -40YC to +85YC +3.0V to +3.6V Supply READ Voltages +2.7V to +3.6V (for battery operated systems) (Functionality is guaranteed between these limits) Stresses above those shown above may cause permanent damage to the device. This is a stress rating only and operation above these specifications for extended periods may affect device reliability. Operation outside the "OPERATING RANGES" shown above voids any and all warranty provisions. DC CHARACTERISTICS FOR READ OPERATION Symbol VOH VOL VIH VIL ILI ILO ICC3 ICC2 ICC1 IPP1 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Power -Down Current VCC Standby Current VCC Active Current VPP Supply Current Read 2.0 -0.3 -5 -10 Min. 2.4 0.45 VCC +0.5 0.8 5 10 10 0.6 15 100 Max. Unit V V V V A A A mA mA A VIN = 0 to 3.6V VOUT = 0 to 3.6V CE = VCC 0.3V CE = VIH CE = VIL, f=5MHz, Conditions IOH = -2.0mA IOL = 2.0mA IOUT = 0mA CE = OE = VIL, VPP = 3.6V CAPACITANCE Symbol CIN COUT CVPP Parameter Input Capacitance Output Capacitance VPP Capacitance Typ. 8 8 18 Max. 12 12 25 Unit pF pF pF Conditions VIN = 0V VOUT = 0V VPP = 0V Tel: 408-235-8680 Fax: 408-235-8685 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 8 Preliminary EN27LV020 / EN27LV020B AC CHARACTERISTICS FOR READ OPERATION EN27LV020 / EN27LV020B Condition CE = OE = VIL OE = VIL OE = VIL -90 Min Max 90 90 45 40 0 Symbol tACC (3) tCE (2) tOE (2, 3) tDF (4, 5) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay -120 -120 Min Max 120 120 45 40 0 -150 -150 Min Max 150 150 50 40 0 -200 -200 Mi Max n 200 200 50 40 0 Unit ns ns ns ns ns OE or CE High to Output Float, whichever occurred first Output Hold from Address, CE or OE , whichever occurred first Note: Please contact Marketing Department for other speed requirements. FIGURE 6. AC WAVEFORMS FOR READ OPERATION ADDRESS ADDRESS VALID CE tCE tOE OE tACC OUTPUT HIGH Z tDF tOH OUTPUT VALID 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 9 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B FIGURE 7: TEST WAVEFORMS AND MEASUREMENTS Output Test Load Input Test Waveform and Measurement Level DC PROGRAMMING CHARACTERISTICS Symbol ILI VIL VIH VOL VOH Iccp IPP2 VID Vcc Vpp Parameter Input Load Current Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Supply Current VPP Supply Current A9 Product Identification Voltage Quikrite Supply Voltage Quikrite Programming Voltage CE = PGM = VIL, Test Conditions VIN = VIL, VIH Min. -0.5 0.7 VCC Limits Max 5.0 0.8 VCC + 0.5 0.45 Units A V V V V IOL = 2.0 mA IOH = - 400 A 2.4 40 10 11.5 6.0 12.5 12.5 6.5 13.0 mA mA V V V 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 10 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B FIGURE 8. PROGRAMMING WAVEFORMS PROGRAM VIH ADDRESS VIL tAS VIH DATA VIL tDS 6.5V VCC 5.0V tVCS 13.0V VPP 5.0V tPRT VIH CE VIL tCES VIH PGM VIL tPW tOES tVPS tDH DATA IN tOE ADDRESS STABLE READ (VERIFY) tAH DATA OUT VALID tDFP VIH OE VIL 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 11 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B SWITCHING PROGRAMMING CHARACTERISTICS (T = + 25 C 5 C) PARAMETER SYMBOL STANDARD PARAMETER DESCRIPTION tAS tOES tDS tAH tDH tDFP tVPS tPW tVCS tCES tOE Address Setup Time OE Setup Time Min. 2 2 2 0 2 0 2 20 2 2 Max Units s s s s s Data Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay VPP Setup Time PGM Program Pulse Width Vcc Setup Time 130 105 ns s s s s CE Setup Time Data Valid from OE 150 ns ORDERING INFORMATION EN27LV020 / EN27LV020B 90 P I TEMPERATURE RANGE (Blank) = Commercial ( 0YC to +70YC) I = Industrial ( -40YC to +85YC) PACKAGE P = 32 Plastic DIP J = 32 Plastic PLCC T = 32 Plastic TSOP SPEED 90 = 90ns 120 = 120ns 150 = 150ns 200 = 200ns BASE PART NUMBER EN = EON Silicon Devices 27 = EPROM LV = Low Voltage CMOS 020 = 256K x 8 3.0V to 3.6V Vcc Tolerance 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 12 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary EN27LV020 / EN27LV020B 020B = 256K x 8 Tolerance 2.7V to 3.6V Vcc 4800 Great America Parkway Ste 202 Santa Clara, CA. 95054 13 Tel: 408-235-8680 Fax: 408-235-8685 Preliminary |
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